PIC12F508/509/16F505
FIGURE 7-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
MCLR Reset
(GP3/RB3)/MCLR/VPP
S
R
Q
Q
MCLRE
WDT Reset
WDT Time-out
Start-up Timer
CHIP Reset
(10 μs or 18 ms)
Pin Change
Sleep
Wake-up on pin Change Reset
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 7-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
© 2007 Microchip Technology Inc.
Preliminary
DS41236C-page 47