PIC12F508/509/16F505
7.3.1
EXTERNAL CLOCK IN
7.3
Reset
For applications where a clock is already available
elsewhere, users may directly drive the PIC12F508/
509/16F505 devices provided that this external clock
source meets the AC/DC timing requirements listed in
Section 7.6 “Watchdog Timer (WDT)”. Figure 7-6
below shows how an external clock circuit should be
configured.
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT time-out Reset during normal operation
• WDT time-out Reset during Sleep
• Wake-up from Sleep on pin change
FIGURE 7-6:
EXTERNAL CLOCK INPUT
OPERATION
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF/GPWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 7-4 for a full description of Reset
states of all registers.
PIC16F505: EC, HS, XT, LP
Clock From
ext. system
RB5/OSC1/CLKIN
PIC16F505
(1)
OSC2/CLKOUT/RB4
OSC2/CLKOUT/RB4
PIC12F508/509: XT, LP
Clock From
ext. system
GP5/OSC1/CLKIN
PIC12F508
PIC12F509
GP4/OSC2
OSC2
Note 1: RB4 is available in EC mode only.
TABLE 7-3:
Register
RESET CONDITIONS FOR REGISTERS – PIC12F508/509
MCLR Reset, WDT Time-out,
Wake-up On Pin Change
Address
Power-on Reset
W
—
qqqq qqqu(1)
xxxx xxxx
xxxx xxxx
1111 1111
qqqq qqqu(1)
uuuu uuuu
uuuu uuuu
1111 1111
INDF
TMR0
PC
00h
01h
02h
STATUS
FSR(4)
03h
04h
0001 1xxx
110x xxxx
q00q quuu(2), (3)
11uu uuuu
FSR(5)
OSCCAL
GPIO
04h
05h
06h
—
111x xxxx
1111 111-
--xx xxxx
1111 1111
--11 1111
111u uuuu
uuuu uuu-
--uu uuuu
1111 1111
--11 1111
OPTION
TRIS
—
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of mem-
ory.
2: See Table 7-8 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: PIC12F508 only.
DS41236C-page 44
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
