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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览
型号: PIC16F767-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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PIC16F7X7
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
Decrement f, Skip if 0
[
label
] DECFSZ f,d
0
f
127
d
[0,1]
(f) – 1
(destination);
skip if result =
0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a
NOP
is
executed instead, making it a
2 T
CY
instruction.
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[
label
]
INCFSZ f,d
0
f
127
d
[0,1]
(f) + 1
(destination),
skip if result =
0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a
NOP
is executed
instead, making it a 2 T
CY
instruction.
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
Unconditional Branch
[
label
]
GOTO k
0
k
2047
k
PC<10:0>
PCLATH<4:3>
PC<12:11>
None
GOTO
is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits<10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>.
GOTO
is a
two-cycle instruction.
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Inclusive OR Literal with W
[
label
]
IORLW k
0
k
255
(W) .OR. k
(W)
Z
The contents of the W register are
ORed with the eight-bit literal ‘k’.
The result is placed in the W
register.
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f
[
label
]
INCF f,d
0
f
127
d
[0,1]
(f) + 1
(destination)
Z
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Inclusive OR W with f
[
label
]
IORWF
f,d
0
f
127
d
[0,1]
(W) .OR. (f)
(destination)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
2004 Microchip Technology Inc.
DS30498C-page 197