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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览
型号: PIC16F767-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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PIC16F7X7
RLF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Rotate Left f through Carry
[
label
] RLF
0
f
127
d
[0,1]
See description below
C
The contents of register ‘f’ are
rotated one bit to the left through the
Carry flag. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
C
Register f
SLEEP
Syntax:
Operands:
Operation:
Enter Sleep mode
[
label
] SLEEP
None
00h
WDT,
0
WDT prescaler,
1
TO,
0
PD
TO, PD
The Power-Down status bit, PD,
is cleared. Time-out status bit,
TO, is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
f,d
Status Affected:
Description:
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Description:
Return from Subroutine
[
label
]
None
TOS
PC
None
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RETURN
SUBLW
Syntax:
Operands:
Operation:
Description:
Subtract W from Literal
[
label
] SUBLW k
0
k
255
k – (W)
→ (W)
The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
Status Affected: C, DC, Z
RRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Rotate Right f through Carry
[
label
]
RRF f,d
0
f
127
d
[0,1]
See description below
C
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
C
Register f
SUBWF
Syntax:
Operands:
Operation:
Description:
Subtract W from f
[
label
] SUBWF f,d
0
f
127
d
[0,1]
(f) – (W)
→ (destination)
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected: C, DC, Z
2004 Microchip Technology Inc.
DS30498C-page 199