PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F7X7

FIGURE 11-11:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT pin

RC6/TX/CK pin

Write to

bit SREN

SREN bit

CREN bit

RCIF bit

(Interrupt)

Read

RXREG

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Note:

Timing diagram demonstrates Sync Master mode with bit SREN =

1

and bit BRG =

0.



2004 Microchip Technology Inc.

DS30498C-page 147