PIC16F7X7
11.4
AUSART Synchronous Slave
Mode
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit, CSRC (TXSTA<7>).
2.
3.
4.
5.
6.
7.
8.
11.4.1
AUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREG and then the
SLEEP
instruction is executed, the following will occur:
a)
b)
c)
d)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG
register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
e)
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
GIE
PSPIF
(1)
SPEN
PSPIE
(1)
Bit 6
PEIE
ADIF
RX9
ADIE
TX9
Bit 5
Bit 4
Bit 3
RBIE
SSPIF
ADDEN
SSPIE
—
Bit 2
TMR0IF
Bit 1
INT0IF
Bit 0
RBIF
Value on:
POR, BOR
0000 000x
Value on
all other
Resets
0000 000u
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend:
Note 1:
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
TMR0IE INT0IE
RCIF
SREN
RCIE
TXEN
TXIF
CREN
TXIE
SYNC
CCP1IF TMR2IF TMR1IF
0000 0000
FERR
OERR
RX9D
0000 000x
0000 0000
CCP1IE TMR2IE TMR1IE
0000 0000
BRGH
TRMT
TX9D
0000 -010
0000 0000
AUSART Transmit Data Register
CSRC
Baud Rate Generator Register
x
= unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS30498C-page 148
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
