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PIC16F777-I/PT 参数 Datasheet PDF下载

PIC16F777-I/PT图片预览
型号: PIC16F777-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
2.2.2.7  
PIR2 Register  
Note:  
Interrupt flag bits are set when an interrupt  
condition occurs regardless of the state of  
its corresponding enable bit or the Global  
Interrupt Enable bit, GIE (INTCON<7>).  
User software should ensure the appropri-  
ate interrupt flag bits are clear prior to  
enabling an interrupt.  
The PIR2 register contains the flag bits for the CCP2  
interrupt.  
REGISTER 2-7:  
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)  
R/W-0  
OSFIF  
R/W-0  
CMIF  
R/W-0  
LVDIF  
U-0  
R/W-0  
BCLIF  
U-0  
R/W-0  
R/W-0  
CCP2IF  
bit 0  
CCP3IF  
bit 7  
bit 7  
bit 6  
bit 5  
OSFIF: Oscillator Fail Interrupt Flag bit  
1= System oscillator failed, clock input has changed to INTRC (must be cleared in software)  
0= System clock operating  
CMIF: Comparator Interrupt Flag bit  
1= Comparator input has changed (must be cleared in software)  
0= Comparator input has not changed  
LVDIF: Low-Voltage Detect Interrupt Flag bit  
1= The supply voltage has fallen below the specified LVD voltage (must be cleared in software)  
0= The supply voltage is greater then the specified LVD voltage  
bit 4  
bit 3  
Unimplemented: Read as ‘0’  
BCLIF: Bus Collision Interrupt Flag bit  
1= A bus collision has occurred in the SSP when configured for I2C Master mode  
0= No bus collision has occurred  
bit 2  
bit 1  
Unimplemented: Read as ‘0’  
CCP3IF: CCP3 Interrupt Flag bit  
Capture mode:  
1= A TMR1 register capture occurred (must be cleared in software)  
0= No TMR1 register capture occurred  
Compare mode:  
1= A TMR1 register compare match occurred (must be cleared in software)  
0= No TMR1 register compare match occurred  
PWM mode:  
Unused in this mode.  
bit 0  
CCP2IF: CCP2 Interrupt Flag bit  
Capture mode:  
1= A TMR1 register capture occurred (must be cleared in software)  
0= No TMR1 register capture occurred  
Compare mode:  
1= A TMR1 register compare match occurred (must be cleared in software)  
0= No TMR1 register compare match occurred  
PWM mode:  
Unused.  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
2004 Microchip Technology Inc.  
DS30498C-page 27  
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