PIC16F7X7
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 and CCP3 peripheral interrupts.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
R/W-0
OSFIE
R/W-0
CMIE
R/W-0
LVDIE
U-0
—
R/W-0
BCLIE
U-0
—
R/W-0
R/W-0
CCP3IE
CCP2IE
bit 7
bit 0
bit 7
bit 6
bit 5
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= LVD interrupt is enabled
0= LVD interrupt is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
BCLIE: Bus Collision Interrupt Enable bit
1= Enable bus collision interrupt in the SSP when configured for I2C Master mode
0= Disable bus collision interrupt in the SSP when configured for I2C Master mode
bit 2
bit 1
Unimplemented: Read as ‘0’
CCP3IE: CCP3 Interrupt Enable bit
1= Enables the CCP3 interrupt
0= Disables the CCP3 interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS30498C-page 26
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
