PIC16F7X7
FIGURE 18-20:
A/D CONVERSION TIMING
BSFADCON0,GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
OLD_DATA
NEW_DATA
DONE
ADRES
ADIF
GO
Sampling Stopped
SAMPLE
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 18-16: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max Units
Conditions
130
TAD
A/D Clock Period PIC16F7X7
1.6
3.0
2.0
3.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF ≥ 2.0V
µs A/D RC mode
µs A/D RC mode
TAD
PIC16LF7X7
PIC16F7X7
PIC16LF7X7
4.0
6.0
—
6.0
9.0
12
131
132
TCNV
TACQ
Conversion Time (not including S/H time)
(Note 1)
Acquisition Time
(Note 2)
40
—
—
—
µs
10*
µs The minimum time is the
amplifier settling time. This may
be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e., 5.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134
TGO
Q4 to A/D Clock Start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.
DS30498C-page 236
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
