PIC16F7X7
TABLE 1-3:
PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)
PDIP
Pin # Pin #
QFN
TQFP I/O/P
Pin # Type
Buffer
Type
Pin Name
Description
PORTD is a bidirectional I/O port or Parallel Slave Port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD0
19
20
21
22
27
28
29
30
38
39
40
41
2
38
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP0
(3)
(3)
(3)
(3)
(3)
(3)
(3)
RD1/PSP1
RD1
39
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
40
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
41
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4
RD4
2
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP4
RD5/PSP5
RD5
3
3
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP5
RD6/PSP6
RD6
4
4
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP6
RD7/PSP7
RD7
5
5
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP7
PORTE is a bidirectional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE0
8
9
25
26
27
31
25
I/O
I
ST/TTL
ST/TTL
ST/TTL
Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.
RD
AN5
I
RE1/WR/AN6
RE1
26
I/O
I
Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.
WR
AN6
I
RE2/CS/AN7
RE2
10
—
27
I/O
I
Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.
CS
AN7
I
VSS
VSS
VDD
VDD
NC
—
6, 29
—
P
P
—
—
—
—
—
Analog ground reference.
12, 31 6, 30
Ground reference for logic and I/O pins.
Analog positive supply.
—
8
P
11, 32 7, 28
7, 28
P
Positive supply for logic and I/O pins.
—
13, 29 12, 13,
33, 34
—
These pins are not internally connected. These pins
should be left unconnected.
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
DS30498C-page 14
2004 Microchip Technology Inc.