PIC16F7X7
FIGURE 11-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
Start
bit
RC7/RX/DT (pin)
Stop
bit
bit 0 bit 1
Stop
bit
bit 8
bit 0
bit 8
Load RSR
Read
Word 1
RCREG
bit 8 = 0, Data Byte
bit 8 = 1, Address Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
FIGURE 11-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
Start
bit
RC7/RX/DT (pin)
Stop
bit
Stop
bit
bit 0 bit 1
bit 8
bit 8
bit 0
Load RSR
Read
Word 1
RCREG
bit 8 = 1, Address Byte
bit 8 = 0, Data Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
TABLE 11-9: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
(1)
0Ch
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA
SREN
CREN ADDEN FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
1Ah
RCREG AUSART Receive Register
(1)
8Ch
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
99h
SPBRG Baud Rate Generator Register
Legend:
x= unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2004 Microchip Technology Inc.
DS30498C-page 143
MICROCHIP [ MICROCHIP ]
