PIC16F62X
8.1
Timer2 Prescaler and Postscaler
8.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
reset.
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
8.2
Output of TMR2
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Sets flag
TMR2
output (1)
bit TMR2IF
Reset
Prescaler
1:1, 1:4, 1:16
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
TMR2 reg
FOSC/4
Postscaler
1:1 to 1:16
2
Comparator
Register 8-1 shows the Timer2 control register.
EQ
4
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
DS40300B-page 54
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
