PIC16F62X
7.5
Resetting Timer1 using a CCP Trigger
Output
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
If the CCP1 module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
resets
0000 000x 0000 000u
0Bh/8Bh/
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh/18Bh
0000 -000 0000 -000
0000 -000 0000 -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Ch
8Ch
0Eh
0Fh
10h
PIR1
EEIF
CMIF
RCIF
TXIF
—
—
CCP1IF TMR2IF
TMR1IF
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE TMR2IE TMR1IE
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 53
MICROCHIP [ MICROCHIP ]
