PIC16F62X
17.5
Timing Diagrams and Specifications
FIGURE 17-6: EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
Fosc External CLKIN Frequency
(Note 1)
DC
—
4
MHz XT and ER osc mode,
VDD=5.0V
DC
DC
—
—
20
MHz HS osc mode
kHz LP osc mode
200
Oscillator Frequency
(Note 1)
—
—
4
4
MHz ER osc mode, VDD=5.0V
0.1
1
MHz XT osc mode
—
—
20
200
MHz HS osc mode
kHz LP osc mode
4
MHz INTRC mode (fast)
kHz INTRC mode (slow)
37
—
—
—
1
Tosc
External CLKIN Period
(Note 1)
250
50
5
—
—
—
ns
ns
µs
XT and ER osc mode
HS osc mode
LP osc mode
Oscillator Period
(Note 1)
250
250
50
—
—
—
—
ns
ER osc mode
10,000 ns
XT osc mode
1,000 ns
HS osc mode
5
µs
ns
µs
LP osc mode
250
27
INTRC mode (fast)
INTRC mode (slow)
TCY = 4/FOSC
2
3
Tcy
Instruction Cycle Time (Note 1) 1.0
TCY
—
DC
—
ns
ns
TosL, External CLKIN (OSC1) High
TosH External CLKIN Low
100 *
XT oscillator, TOSC L/H duty
cycle
4
5
INTRC Internal Calibrated ER
3.65
4.00
4.28
MHz VDD = 5.0V
VDD = 5.0V
ER
External Biased ER Frequency 10kHz
8MHz
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 139
MICROCHIP [ MICROCHIP ]
