PIC16F62X
FIGURE 17-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 17-9: BROWN-OUT DETECT TIMING
BVDD
VDD
35
TABLE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
30
TmcL MCLR Pulse Width (low)
2000
TBD
—
TBD
—
TBD
ns
VDD = 5V, -40°C to +85°C
ms Extended temperature
31
Twdt
Tost
Watchdog Timer Time-out Period
(No Prescaler)
7
TBD
18
TBD
33
TBD
ms VDD = 5V, -40°C to +85°C
ms Extended temperature
32
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt Power up Timer Period
28
72
132
ms VDD = 5V, -40°C to +85°C
TBD
TBD
TBD
ms
34
35
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.0
µs
TBOD
Brown-out Detect pulse width
100
—
—
µs
VDD ≤ BVDD (D005)
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 141