PIC16F62X
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
14.6
Interrupts
The PIC16F62X has 10 sources of interrupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PortB Change Interrupts (pins RB7:RB4)
• Comparator Interrupt
• USART Interrupt
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 14-17). The latency is the same for one or two
cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by poll-
ing the interrupt flag bits. The interrupt flag bit(s) must
be cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
• CCP Interrupt
• TMR1 Overflow Interrupt
• TMR2 Match Interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP in the cycle immediately following
the instruction which clears the GIE bit.
The interrupts which were ignored are
still pending to be serviced when the GIE
bit is set again.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 14-16: INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
Interrupt to CPU
T0IF
T0IE
TMR1IF
TMR1IE
INTF
INTE
TMR2IF
TMR2IE
RBIF
RBIE
CCP1IF
CCP1IE
CMIF
CMIE
PEIE
TXIF
TXIE
GIE
RCIF
RCIE
EEIF
EEIE
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 107
MICROCHIP [ MICROCHIP ]
