PIC16F62X
FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M
U
X
Postscaler
8
1
Watchdog
Timer
•
PS<2:0>
To TMR0 (Figure 6-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on Value on
POR
Reset
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
OPTION
LVP
BOREN
INTEDG
MCLRE
T0CS
FOSC2
T0SE
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
RBPU
Legend: Shaded cells are not used by the Watchdog Timer.
Note: _ = Unimplemented location, read as “0”
+ = Reserved for future use
DS40300B-page 110
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
