PIC16C745/765
9.2
Compare Mode
9.3
PWM Mode (PWM)
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
Figure 9-3 shows a simplified block diagram of the CCP
module in PWM mode.
FIGURE 9-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Special Event Trigger
CCP1CON<5:4>
Set flag bit CCP1IF
(PIR1<2>)
Duty Cycle Registers
CCPR1L
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
TRISC<2>
Output Enable
CCPR1H (Slave)
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Q
R
S
Comparator
9.2.1
CCP PIN CONFIGURATION
RC2/CCP1
(Note 1)
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
TMR2
TRISC<2>
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
9.2.2
TIMER1 MODE SELECTION
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 9-4) has a time base (period) and
a time that the output stays high (duty cycle). The fre-
quency of the PWM is the inverse of the period (1/period).
9.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
FIGURE 9-4: PWM OUTPUT
Period
9.2.4
SPECIAL EVENT TRIGGER
CCP1(2)
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Duty Cycle
(1)
The special event trigger output of CCP1 resets the TMR1
register pair. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
(1)
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
DS41124A-page 54
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
