PIC16C71X
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
[ label ] RETFIE
None
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
NOP
NOP
NOP
Words:
1
2
NOP
Example
Cycles:
Q Cycle Activity:
1st Cycle
Q1
Q2
Q3
Q4
Decode
NOP
Set the Pop from
GIE bit the Stack
NOP
NOP
NOP
NOP
2nd Cycle
Example
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Operands:
Operation:
(W) → OPTION
Status Affected: None
00
0000
0110
0010
Encoding:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Description:
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
1997 Microchip Technology Inc.
DS30272A-page 79
MICROCHIP [ MICROCHIP ]
