PIC16C71X
IORWF
Inclusive OR W with f
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
k → (W)
Operation:
(W) .OR. (f) → (dest)
None
Status Affected:
Encoding:
Z
11
00xx
kkkk
kkkk
00
0100
dfff
ffff
The eight bit literal 'k' is loaded into W
register.The don’t cares will assemble
as 0’s.
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
Decode
Read
register
'f'
Process
data
Write to
dest
MOVLW
0x5A
Example
After Instruction
IORWF
RESULT, 0
Example
W
=
0x5A
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
1
W
Z
=
=
MOVWF
Move W to f
MOVF
Move f
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ f ≤ 127
d
[0,1]
None
Operation:
(f) → (dest)
00
0000
1fff
ffff
Status Affected:
Encoding:
Z
Move data from W register to register
'f'.
00
1000
dfff
ffff
The contents of register f is moved to
a destination dependant upon the sta-
tus of d. If d = 0, destination is W reg-
ister. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
Words:
1
1
Cycles:
MOVWF
OPTION_REG
Example
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
OPTION =
Decode
Read
register
'f'
Process
data
Write to
dest
0xFF
0x4F
W
=
After Instruction
OPTION =
0x4F
0x4F
MOVF
FSR, 0
Example
W
=
After Instruction
W = value in FSR register
Z
= 1
DS30272A-page 78
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
