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PIC16C715-04E/SS 参数 Datasheet PDF下载

PIC16C715-04E/SS图片预览
型号: PIC16C715-04E/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器与A / D转换器 [8-Bit CMOS Microcontrollers with A/D Converter]
分类和应用: 转换器微控制器
文件页数/大小: 176 页 / 1596 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C71X  
8.5.1  
INT INTERRUPT  
8.5.2  
TMR0 INTERRUPT  
External interrupt on RB0/INT pin is edge triggered:  
either rising if bit INTEDG (OPTION<6>) is set, or fall-  
ing, if the INTEDG bit is clear. When a valid edge  
appears on the RB0/INT pin, flag bit INTF  
(INTCON<1>) is set. This interrupt can be disabled by  
clearing enable bit INTE (INTCON<4>). Flag bit INTF  
must be cleared in software in the interrupt service rou-  
tine before re-enabling this interrupt. The INT interrupt  
can wake-up the processor from SLEEP, if bit INTE was  
set prior to going into SLEEP.The status of global inter-  
rupt enable bit GIE decides whether or not the proces-  
sor branches to the interrupt vector following wake-up.  
See Section 8.8 for details on SLEEP mode.  
An overflow (FFh 00h) in the TMR0 register will set  
flag bit T0IF (INTCON<2>). The interrupt can be  
enabled/disabled by setting/clearing enable bit T0IE  
(INTCON<5>). (Section 6.0)  
8.5.3  
PORTB INTCON CHANGE  
An input change on PORTB<7:4> sets flag bit RBIF  
(INTCON<0>). The interrupt can be enabled/disabled  
by setting/clearing enable bit RBIE (INTCON<4>).  
(Section 5.2)  
Note: For the PIC16C71  
if a change on the I/O pin should occur  
when the read operation is being executed  
(start of the Q2 cycle), then the RBIF inter-  
rupt flag may not get set.  
FIGURE 8-19: INT PIN INTERRUPT TIMING  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
CLKOUT  
3
4
INT pin  
1
1
Interrupt Latency  
INTF flag  
(INTCON<1>)  
5
2
GIE bit  
(INTCON<7>)  
INSTRUCTION FLOW  
PC  
0004h  
PC+1  
PC+1  
0005h  
PC  
Instruction  
fetched  
Inst (PC)  
Inst (PC+1)  
Inst (0004h)  
Inst (0005h)  
Inst (0004h)  
Instruction  
executed  
Dummy Cycle  
Dummy Cycle  
Inst (PC)  
Inst (PC-1)  
Note  
1: INTF flag is sampled here (every Q1).  
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.  
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.  
3: CLKOUT is available only in RC oscillator mode.  
4: For minimum width of INT pulse, refer to AC specs.  
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.  
1997 Microchip Technology Inc.  
DS30272A-page 63  
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