PIC16C71X
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 8-19).
The latency is the same for one or two cycle instruc-
tions. Individual interrupt flag bits are set regardless of
the status of their corresponding mask bit or the GIE
bit.
8.5
Interrupts
Applicable Devices 710 71 711 715
The PIC16C71X family has 4 sources of interrupt.
Interrupt Sources
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
A/D Interrupt
Note: For the PIC16C71
If an interrupt occurs while the Global Inter-
rupt Enable (GIE) bit is being cleared, the
GIE bit may unintentionally be re-enabled
by the user’s Interrupt Service Routine (the
RETFIE instruction). The events that
would cause this to occur are:
The interrupt control register (INTCON) records indi-
vidual interrupt requests in flag bits. It also has individ-
ual and global interrupt enable bits.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
1. An instruction clears the GIE bit while
an interrupt is acknowledged.
2. The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
3. The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF
INTCON, GIE ; Disable global
interrupt bit
BTFSC INTCON, GIE ; Global interrupt
disabled?
; NO, try again
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
;
;
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2.The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
GOTO LOOP
:
;
;
;
Yes, continue
with program
flow
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
1997 Microchip Technology Inc.
DS30272A-page 61
MICROCHIP [ MICROCHIP ]
