PIC16C63A/65B/73B/74B
7.1
Timer1 Operation in Timer Mode
7.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
OSC
/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
TMR1H
TMR1
TMR1L
0
1
TMR1ON
On/Off
T1SYNC
Synchronized
Clock Input
T1OSC
RC0/T1OSO/T1CKI
(2)
1
T1OSCEN F
OSC
/4
Enable
Internal
Oscillator
(1)
Clock
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
TMR1CS
Synchronize
det
SLEEP Input
RC1/T1OSI/CCP2
(2)
Note 1:
When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2:
For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in External Clock mode.
DS30605C-page 44
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
