PIC16C63A/65B/73B/74B
TABLE C-2:
Param
No.
Core
D001
D001A
D005
D150*
SPECIFICATION DIFFERENCES
PIC16C63/65A/73A/74A
PIC16C63A/65B/73B/74B
Unit
Min
Typ†
—
—
4.0
—
Symbol
Characteristic
Max
6.0
—
4.3
14.0
Min
4.0
V
BOR(1)
3.65
-
Typ†
—
—
—
—
Max
5.5
5.5
4.35
8.5
V
V
V
V
V
DD
B
VDD
V
OD
Supply Voltage
Brown-out Reset Voltage
Open-Drain High Voltage on
RA4
Reference voltage
Conversion time
(Note 2)
(not including S/H time)
4.0
—
3.7
—
A/D Converter
A20
V
REF
131
T
CNV
SSP in SPI mode
71
TscH
71A
72
TscL
72A
73
TdiV2scH
TdiV2scL
T
B
2
B
3.0
—
—
V
DD
+ 0.3
9.5
—
(Note 3)
—
—
—
—
2.5
11
(Note 4)
1.25T
CY
+ 30
40
1.25T
CY
+ 30
40
100
1.5T
CY
+ 40
100
—
—
—
—
—
—
—
—
V
DD
+ 0.3 V
11
T
AD
(Note 4)
—
—
—
—
—
—
—
25
45
25
45
50
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
73A
(Note 5)
74
TscH2diL
TscL2diL
75
TdoR
78
TscR
80
TscH2doV
TscL2doV
83
—
50
1.5T
CY
+ 40
—
—
ns
TscH2ssH
TscL2ssH
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
When BOR is enabled, the device will operate until V
DD
drops below V
BOR
.
ADRES register may be read on the following T
CY
cycle.
This is the time that the actual conversion requires.
This is the time from when the GO/DONE bit is set, to when the conversion result appears in ADRES.
Specification 73A is only required if specifications 71A and 72A are used.
SCK input high
Continuous T
CY
+20
time (Slave mode) Single Byte
SCK input low
Continuous T
CY
+20
time
Single Byte
(Slave mode)
Setup time of SDI data input to
50
SCK edge
Last clock edge of Byte1 to the
—
1st clock edge of Byte2
Hold time of SDI data input to
50
SCK edge
SDO data output PIC16CXX
—
rise time
PIC16LCXX
SCK output rise
PIC16CXX
—
time (Master
PIC16LCXX
mode)
SDO data output PIC16CXX
—
valid after SCK
PIC16LCXX
edge
—
SS
↑
after SCK edge
—
—
—
—
—
—
—
10
20
10
20
—
—
—
—
—
10
10
—
—
—
25
25
—
50
Note 1:
2:
3:
4:
5:
2000 Microchip Technology Inc.
DS30605C-page 167
MICROCHIP [ MICROCHIP TECHNOLOGY ]
