PIC16C63A/65B/73B/74B
FIGURE 16-20:
A/D CONVERSION TIMING
1 T
CY
(T
OSC
/2)
(1)
BSF ADCON0, GO
134
Q4
130
A/D CLK
132
131
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
GO
SAMPLING STOPPED
DONE
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
TABLE 16-17: A/D CONVERSION REQUIREMENTS
Param
Sym
No.
130
T
AD
Characteristic
A/D clock period
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
131
132
T
CNV
Conversion time (not including S/H
time)
(Note 1)
T
ACQ
Acquisition time
Min
1.6
2.0
2.0
3.0
11
5*
Typ†
—
—
4.0
6.0
—
—
Max
—
—
6.0
9.0
11
—
Units
µs
µs
µs
µs
T
AD
µs
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0mV @ 5.12V) from
the last sampled voltage (as
stated on C
HOLD
).
If the A/D clock source is
selected as RC, a time of T
CY
is added before the A/D clock
starts. This allows the
SLEEP
instruction to be executed.
Conditions
T
OSC
based, V
REF
≥
3.0 V
T
OSC
based,
2.5V
≤
V
REF
≤
5.5 V
A/D RC mode
A/D RC mode
134
T
GO
Q4 to A/D clock start
—
T
OSC
/2
—
—
135
T
SWC
Switching from convert
→
sample time
1.5
—
—
T
AD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1:
ADRES register may be read on the following T
CY
cycle.
2:
See Section 12.1 for minimum conditions.
DS30605C-page 138
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
