PIC16C63A/65B/73B/74B
FIGURE 16-18:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
120
Note:
121
121
122
Refer to Figure 16-4 for load conditions.
TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
120*
Sym
TckH2dtV
Characteristic
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Clock out rise time and fall
time (Master mode)
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
Min
—
—
—
—
—
—
Typ†
—
—
—
—
—
—
Max
80
100
45
50
45
50
Units Conditions
ns
ns
ns
ns
ns
ns
121*
Tckrf
122*
Tdtrf
Data out rise time and fall time PIC16CXX
PIC16LCXX
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
FIGURE 16-19:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note:
Refer to Figure 16-4 for load conditions.
TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
125*
Sym
TdtV2ckL
Characteristic
SYNC RCV (MASTER & SLAVE)
Data setup before CK
↓
(DT setup
time)
Data hold after CK
↓
(DT hold time)
Min
Typ†
Max
Units
Conditions
15
15
—
—
—
—
ns
ns
126*
TckL2dtl
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 136
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
