PIC16C63A/65B/73B/74B
TABLE 16-13: I
2
C BUS DATA REQUIREMENTS
Param.
No.
100*
Sym
T
HIGH
Characteristic
Clock high time
100 kHz mode
400 kHz mode
SSP Module
101*
T
LOW
Clock low time
100 kHz mode
400 kHz mode
SSP Module
102*
T
R
SDA and SCL rise
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Min
4.0
0.6
1.5T
CY
4.7
1.3
1.5T
CY
—
20 + 0.1Cb
—
20 + 0.1Cb
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
Max
—
—
—
—
—
—
1000
300
300
300
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
400
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
pF
Time the bus must be free
before a new transmission
can start
(Note 1)
(Note 2)
Cb is specified to be from
10-400 pF
Only relevant for Repeated
START condition
After this period the first
clock pulse is generated
Cb is specified to be from
10-400 pF
µs
µs
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Units
µs
µs
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
103*
T
F
SDA and SCL fall
time
90*
T
SU
:
STA
START condition
setup time
START condition
hold time
91*
T
HD
:
STA
106*
T
HD
:
DAT
Data input hold time 100 kHz mode
400 kHz mode
107*
T
SU
:
DAT
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
92*
T
SU
:
STO
109*
T
AA
110*
T
BUF
Cb
Bus capacitive loading
* These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast mode (400 kHz) I
2
C bus device can be used in a standard mode (100 kHz) I
2
C bus system, but the
requirement Tsu:DAT
≥
250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line T
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the stan-
dard mode I
2
C bus specification) before the SCL line is released.
2000 Microchip Technology Inc.
DS30605C-page 135
MICROCHIP [ MICROCHIP TECHNOLOGY ]
