欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F684-I/P 参数 Datasheet PDF下载

PIC16F684-I/P图片预览
型号: PIC16F684-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 164 页 / 2585 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F684-I/P的Datasheet PDF文件第76页浏览型号PIC16F684-I/P的Datasheet PDF文件第77页浏览型号PIC16F684-I/P的Datasheet PDF文件第78页浏览型号PIC16F684-I/P的Datasheet PDF文件第79页浏览型号PIC16F684-I/P的Datasheet PDF文件第81页浏览型号PIC16F684-I/P的Datasheet PDF文件第82页浏览型号PIC16F684-I/P的Datasheet PDF文件第83页浏览型号PIC16F684-I/P的Datasheet PDF文件第84页  
PIC16F684  
Figure 11-3 shows a simplified block diagram of PWM  
operation.  
11.3 Enhanced PWM Mode  
The Enhanced CCP module produces up to a 10-bit  
resolution PWM output and may have up to four  
outputs, depending on the selected operating mode.  
These outputs, designated P1A through P1D, are  
multiplexed with I/O pins on PORTC. The pin  
assignments are summarized in Table 11-3.  
To configure I/O pins as PWM outputs, the proper PWM  
mode must be selected by setting the P1M<1:0> and  
CCP1M<3:0>  
bits  
(CCP1CON<7:6>  
and  
CCP1CON<3:0>, respectively). The appropriate  
TRISC bits must also be set as outputs.  
FIGURE 11-3:  
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE  
CCP1CON<5:4>  
P1M<1:0>  
CCP1M<3:0>  
4
Duty Cycle Registers  
2
CCPR1L  
CCP1/P1A  
RC5/CCP1/P1A  
TRISC<5>  
TRISC<4>  
TRISC<3>  
TRISC<2>  
CCPR1H (Slave)  
Comparator  
P1B  
RC4/C2OUT/P1B  
RC3/AN7/P1C  
Output  
R
Q
Controller  
P1C  
(1)  
TMR2  
S
P1D  
RC2/AN6/P1D  
Comparator  
PR2  
Clear Timer2,  
toggle PWM pin and  
latch duty cycle  
PWM1CON  
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to  
create the 10-bit time base.  
The general relationship of the outputs in all  
configurations is summarized in Figure 11-3.  
11.3.1  
PWM OUTPUT CONFIGURATIONS  
The P1M<1:0> bits in the CCP1CON register allows  
one of four configurations:  
Note:  
Clearing the CCP1CON register will force  
the PWM output latches to their default  
inactive levels. This is not the PORTC I/O  
data latch.  
• Single Output  
• Half-bridge Output  
• Full-bridge Output, Forward mode  
• Full-bridge Output, Reverse mode  
TABLE 11-3: PIN ASSIGNMENTS FOR VARIOUS ENHANCED CCP MODES  
CCP1CON  
ECCP Mode  
RC5  
RC4  
RC3  
RC2  
Configuration  
Compatible CCP  
00xx11xx  
10xx11xx  
x1xx11xx  
CCP1  
P1A  
RC4/C2OUT  
P1B  
RC3/AN7  
RC3/AN7  
P1C  
RC2/AN6  
RC2/AN6  
P1D  
Dual PWM  
Quad PWM  
P1A  
P1B  
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.  
Note 1: TRIS register values must be configured appropriately.  
2: With ECCP in Dual or Quad PWM mode, the C2OUT output control of PORTC must be disabled.  
DS41202C-page 78  
Preliminary  
2004 Microchip Technology Inc.