PIC16F684
The following equation is used to calculate the PWM
duty cycle in time:
11.3.2
PWM PERIOD
A PWM output (Figure 11-4 and Figure 11-5) has a time
base (period) and a time that the output is active (duty
cycle). The PWM period is specified by writing to the
PR2 register. The PWM period can be calculated using
the following formula:
EQUATION 11-2:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC
• (TMR2 prescale value)
EQUATION 11-1:
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the appropriate PWM pin is
toggled. In Dual PWM mode, the pin will be toggled
after the dead band time has expired.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
The polarity (active-high or active-low) and mode of the
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
signal
(CCP1CON<7:6>)
are
configured
by
and
the
P1M<1:0>
CCP1M<3:0>
• TMR2 is cleared
(CCP1CON<3:0>) bits.
• The appropriate PWM pin toggles. In Dual PWM
mode, this occurs after the dead band delay
expires (exception: if PWM duty cycle = 0%, the
pin will not be set)
The maximum PWM resolution for a given PWM
frequency is given by the formula:
EQUATION 11-3:
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FOSC
------------------------------------------------------------
log
FPWM • TMR2 Prescaler
--------------------------------------------------------------------------
Resolution =
bits
log(2)
Note:
The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
All control registers are double buffered and are loaded
at the beginning of a new PWM cycle (the period
boundary when Timer2 resets) in order to prevent
glitches on any of the outputs. The exception is the
PWM delay register, which is loaded at either the duty
cycle boundary or the period boundary (whichever
comes first). Because of the buffering, the module
waits until the timer resets, instead of starting immedi-
ately. This means that enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead offset by one full instruction cycle (4 TOSC).
11.3.3
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the DC1B<1:0>
(CCP1CON<5:4>) bits. Up to 10 bits of resolution is
available. The CCPR1L contains the eight MSbs and
the DC1B<1:0> contains the two LSbs. CCPR1L and
DC1B<1:0> can be written to at any time. In PWM
mode, CCPR1H is a read-only register. This 10-bit
value is represented by CCPR1L (CCP1CON<5:4>).
Note:
If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz(1)
4.88 kHz(1)
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
Note 1: Changing duty cycle will cause a glitch.
2004 Microchip Technology Inc.
Preliminary
DS41202C-page 79
MICROCHIP [ MICROCHIP ]
