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PIC16F684-I/P 参数 Datasheet PDF下载

PIC16F684-I/P图片预览
型号: PIC16F684-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 164 页 / 2585 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F684  
10.5 Protection Against Spurious Write  
10.6 Data EEPROM Operation During  
Code-Protect  
There are conditions when the user may not want to  
write to the data EEPROM memory. To protect against  
spurious EEPROM writes, various mechanisms have  
been built in. On power-up, WREN is cleared. Also, the  
Data memory can be code-protected by programming  
the CPD bit in the Configuration Word register  
(Register 12-1) to ‘0’.  
Power-up  
Timer  
(64 ms  
duration)  
prevents  
When the data memory is code-protected, the CPU is  
able to read and write data to the data EEPROM. It is  
recommended to code-protect the program memory  
when code-protecting data memory. This prevents  
anyone from programming zeroes over the existing  
code (which will execute as NOPs) to reach an added  
routine, programmed in unused program memory,  
which outputs the contents of data memory.  
Programming unused locations in program memory to  
0’ will also help prevent data memory code protection  
from becoming breached.  
EEPROM write.  
The write initiate sequence and the WREN bit together  
help prevent an accidental write during:  
• Brown-out  
• Power Glitch  
• Software Malfunction  
TABLE 10-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM  
Value on  
all other  
Resets  
Value on  
POR, BOD  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0Bh/8Bh  
0Ch  
INTCON  
PIR1  
GIE  
EEIF  
EEIE  
PEIE  
ADIF  
ADIE  
T0IE  
INTE  
C2IF  
C2IE  
RAIE  
C1IF  
C1IE  
T0IF  
INTF  
RAIF 0000 0000 0000 0000  
CCP1IF  
CCP1IE  
OSFIF TMR2IF TMR1IF 0000 0000 0000 0000  
OSFIE TMR2IE TMR1IE 0000 0000 0000 0000  
8Ch  
PIE1  
9Ah  
EEDAT  
EEADR  
EECON1  
EECON2  
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000  
EEADR7 EEADR6 EEADR5 EEADR EEADR EEADR EEADR EEADR 0000 0000 0000 0000  
9Bh  
9Ch  
WRERR WREN  
WR  
RD  
---- x000 ---- q000  
---- ---- ---- ----  
(1)  
9Dh  
EEPROM Control register 2  
Legend:  
x= unknown, u= unchanged, — = unimplemented read as ‘0’, q= value depends upon condition.  
Shaded cells are not used by data EEPROM module.  
Note 1: EECON2 is not a physical register.  
DS41202C-page 74  
Preliminary  
2004 Microchip Technology Inc.