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PIC16F627-20/P 参数 Datasheet PDF下载

PIC16F627-20/P图片预览
型号: PIC16F627-20/P
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)  
R/W-0  
SPEN  
R/W-0  
RX9  
R/W-0  
SREN  
R/W-0  
CREN  
R/W-0  
ADEN  
R-0  
R-0  
R-x  
FERR  
OERR  
RX9D  
R = Readable bit  
W = Writable bit  
U = Unimplemented bit,  
read as ’0’  
bit7  
bit0  
-n = Value at POR reset  
x = unknown  
bit 7:  
SPEN: Serial Port Enable bit  
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)  
1= Serial port enabled  
0= Serial port disabled  
bit 6:  
RX9: 9-bit Receive Enable bit  
1= Selects 9-bit reception  
0= Selects 8-bit reception  
bit 5:  
SREN: Single Receive Enable bit  
Asynchronous mode:  
Don’t care  
Synchronous mode - master:  
1= Enables single receive  
0= Disables single receive  
This bit is cleared after reception is complete.  
Synchronous mode - slave:  
Unused in this mode  
bit 4:  
CREN: Continuous Receive Enable bit  
Asynchronous mode:  
1= Enables continuous receive  
0= Disables continuous receive  
Synchronous mode:  
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)  
0= Disables continuous receive  
bit 3:  
ADEN: Address Detect Enable bit  
Asynchronous mode 9-bit (RX9 = 1):  
1= Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set  
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit  
Asynchronous mode 8-bit (RX9=0):  
Unused in this mode  
Synchronous mode  
Unused in this mode  
bit 2:  
bit 1:  
bit 0:  
FERR: Framing Error bit  
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)  
0= No framing error  
OERR: Overrun Error bit  
1= Overrun error (Can be cleared by clearing bit CREN)  
0= No overrun error  
RX9D: 9th bit of received data (Can be parity bit)  
DS40300B-page 72  
Preliminary  
1999 Microchip Technology Inc.