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PIC16F627-20/P 参数 Datasheet PDF下载

PIC16F627-20/P图片预览
型号: PIC16F627-20/P
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
EXAMPLE 11-1: VOLTAGE REFERENCE  
CONFIGURATION  
11.4  
Effects of a Reset  
A device reset disables the Voltage Reference by clear-  
ing bit VREN (VRCON<7>). This reset also disconnects  
the reference from the RA2 pin by clearing bit VROE  
(VRCON<6>) and selects the high voltage range by  
clearing bit VRR (VRCON<5>). The VREF value select  
bits, VRCON<3:0>, are also cleared.  
MOVLW  
MOVWF  
BSF  
0x02  
; 4 Inputs Muxed  
; to 2 comps.  
; go to Bank 1  
; RA3-RA0 are  
; outputs  
CMCON  
STATUS,RP0  
0x07  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
TRISA  
0xA6  
; enable VREF  
; low range  
11.5  
Connection Considerations  
Voltage Reference Module  
VRCON  
; set VR<3:0>=6  
; go to Bank 0  
; 10µs delay  
The  
operates  
independently of the comparator module. The output of  
the reference generator may be connected to the RA2  
pin if the TRISA<2> bit is set and the VROE bit,  
VRCON<6>, is set. Enabling the Voltage Reference  
output onto the RA2 pin with an input signal present will  
increase current consumption. Connecting RA2 as a  
digital output with VREF enabled will also increase  
current consumption.  
BCF  
STATUS,RP0  
DELAY10  
CALL  
11.2  
Voltage Reference Accuracy/Error  
The full range of VSS to VDD cannot be realized due to  
the construction of the module. The transistors on the  
top and bottom of the resistor ladder network  
(Figure 11-2) keep VREF from approaching VSS or VDD.  
The Voltage Reference is VDD derived and therefore,  
the VREF output changes with fluctuations in VDD. The  
tested absolute accuracy of the Voltage Reference can  
be found in Table 17-2.  
The RA2 pin can be used as a simple D/A output with  
limited drive capability. Due to the limited drive  
capability, a buffer must be used in conjunction with the  
Voltage Reference output for external connections to  
VREF. Figure 11-3 shows an example buffering  
technique.  
11.3  
Operation During Sleep  
When the device wakes up from sleep through an  
interrupt or a Watchdog Timer time-out, the contents of  
the VRCON register are not affected. To minimize  
current consumption in SLEEP mode, the Voltage  
Reference should be disabled.  
FIGURE 11-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE  
(1)  
RA2  
R
VREF  
Module  
+
VREF Output  
Voltage  
Reference  
Output  
Impedance  
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.  
TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE  
Value On  
Value On  
All Other  
Resets  
Address Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
POR  
9Fh  
1Fh  
85h  
VRCON  
VREN  
VROE  
VRR  
VR3  
CIS  
VR2  
CM2  
VR1  
CM1  
VR0  
CM0  
000- 0000 000- 0000  
0000 0000 0000 0000  
CMCON C2OUT C1OUT C2INV  
TRISA TRISA7 TRISA6  
C1INV  
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111  
Note: -= Unimplemented, read as "0"  
DS40300B-page 70  
Preliminary  
1999 Microchip Technology Inc.