PIC16CE62X
disable (if set) or enable (if cleared or programmed) the
Power-up Timer.The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
10.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters for details.
10.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A maximum rise time for VDD
is required. See Electrical Specifications for details.
10.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
The POR circuit does not produce internal reset when
VDD declines.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
10.4.4 BROWN-OUT RESET (BOR)
The PIC16CE62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BODEN, can dis-
able (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If VDD falls below 4.0V (refer
to BVDD parameter D005) for greater than parameter
(TBOR) in Table 13-6, the brown-out situation will reset
the chip. A reset is not guaranteed to occur if VDD falls
below 4.0V for less than parameter (TBOR). The chip
will remain in Brown-out Reset until VDD rises above
BVDD.The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms. If VDD drops
below BVDD while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above BVDD, the Power-Up Timer will execute a 72 ms
reset. The Power-up Timer should always be enabled
when Brown-out Reset is enabled. Figure 10-8 shows
typical Brown-out situations.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
10.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset.The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
FIGURE 10-8: BROWN-OUT SITUATIONS
VDD
BVDD
Internal
Reset
72 ms
VDD
BVDD
Internal
Reset
<72 ms
72 ms
VDD
BVDD
Internal
Reset
72 ms
DS40182A-page 54
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
