PIC16CE62X
state” on Power-on reset, on MCLR or WDT reset and
on MCLR reset during SLEEP.They are not affected by
a WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 10-4. These bits are used in software to deter-
mine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
10.3
Reset
The PIC16CE62X differentiates between various kinds
of reset:
a) Power-on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT reset (normal operation)
e) WDT wake-up (SLEEP)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-7.
f) Brown-out Reset (BOR)
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 13-6 for pulse width
specification.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
10-bit Ripple-counter
Chip_Reset
Q
OSC1/
CLKIN
Pin
PWRT
10-bit Ripple-counter
(1)
On-chip
RC OSC
Enable PWRT
Enable OST
See Table 10-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 53
MICROCHIP [ MICROCHIP ]
