PIC16F87XA
4.0
I/O PORTS
EXAMPLE 4-1:
BCF
BCF
CLRF
INITIALIZING PORTA
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Bank0
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6>are always
read as ’0’.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
STATUS, RP0
STATUS, RP1
PORTA
4.1
PORTA and the TRISA Register
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog V
REF
input for both the A/D converters
and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits
in the ADCON1 and/or CMCON registers.
Note:
On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
The comparators are in the Off (digital)
state.
MOVWF
TRISA
FIGURE 4-1:
Data
Bus
Data Latch
D
Q
BLOCK DIAGRAM OF
RA3:RA0 PINS
WR
PORTA
V
DD
CK
Q
P
I/O pin
(1)
TRIS Latch
D
WR
TRISA
Q
N
CK
Q
V
SS
Analog
Input
Mode
RD
TRISA
TTL
Input
Buffer
Q
D
The TRISA register controls the direction of the port
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EN
RD PORTA
To A/D Converter or Comparator
Note 1:
I/O pins have protection diodes to V
DD
and V
SS
.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 39
MICROCHIP [ MICROCHIP TECHNOLOGY ]
