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PIC16F873A-I/SP 参数 Datasheet PDF下载

PIC16F873A-I/SP图片预览
型号: PIC16F873A-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
FIGURE 4-10:  
PORTD AND PORTE  
BLOCK DIAGRAM  
(PARALLEL SLAVE  
PORT)  
4.6  
Parallel Slave Port  
The Parallel Slave Port (PSP) is not implemented on  
the PIC16F873A or PIC16F876A.  
PORTD operates as an 8-bit wide Parallel Slave Port or  
microprocessor port, when control bit PSPMODE  
(TRISE<4>) is set. In Slave mode, it is asynchronously  
readable and writable by the external world through RD  
control input pin, RE0/RD and WR control input pin,  
RE1/WR.  
Data Bus  
D
Q
WR  
Port  
RDx  
pin  
CK  
TTL  
The PSP can directly interface to an 8-bit micro-  
processor data bus. The external microprocessor can  
read or write the PORTD latch as an 8-bit latch. Setting  
bit PSPMODE enables port pin RE0/RD to be the RD  
input, RE1/WR to be the WR input and RE2/CS to be  
the CS (chip select) input. For this functionality, the cor-  
responding data direction bits of the TRISE register  
(TRISE<2:0>) must be configured as inputs (set). The  
Q
D
RD  
Port  
EN  
One bit of PORTD  
Set Interrupt Flag  
PSPIF(PIR1<7>)  
A/D  
port  
configuration  
bits,  
PCFG3:PCFG0  
(ADCON1<3:0>), must be set to configure pins  
RE2:RE0 as digital I/O.  
There are actually two 8-bit latches: one for data out-  
put, and one for data input. The user writes 8-bit data  
to the PORTD data latch and reads data from the port  
pin latch (note that they have the same address). In this  
mode, the TRISD register is ignored, since the external  
device is controlling the direction of data flow.  
Read  
TTL  
RD  
CS  
WR  
Chip Select  
TTL  
Write  
TTL  
A write to the PSP occurs when both the CS and WR  
lines are first detected low. When either the CS or WR  
lines become high (level triggered), the Input Buffer Full  
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock  
cycle, following the next Q2 cycle, to signal the write is  
complete (Figure 4-11). The interrupt flag bit PSPIF  
(PIR1<7>) is also set on the same Q4 clock cycle. IBF  
can only be cleared by reading the PORTD input latch.  
The Input Buffer Overflow (IBOV) status flag bit  
(TRISE<5>) is set if a second write to the PSP is  
attempted when the previous byte has not been read  
out of the buffer.  
Note 1: I/O pins have protection diodes to VDD and VSS.  
A read from the PSP occurs when both the CS and RD  
lines are first detected low. The Output Buffer Full  
(OBF) status flag bit (TRISE<6>) is cleared immedi-  
ately (Figure 4-12), indicating that the PORTD latch is  
waiting to be read by the external bus. When either the  
CS or RD pin becomes high (level triggered), the inter-  
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-  
ing the next Q2 cycle, indicating that the read is  
complete. OBF remains low until data is written to  
PORTD by the user firmware.  
When not in PSP mode, the IBF and OBF bits are held  
clear. However, if flag bit IBOV was previously set, it  
must be cleared in firmware.  
An interrupt is generated and latched into flag bit  
PSPIF when a read or write operation is completed.  
PSPIF must be cleared by the user in firmware and the  
interrupt can be disabled by clearing the interrupt  
enable bit PSPIE (PIE1<7>).  
2001 Microchip Technology Inc.  
Advance Information  
DS39582A-page 49