PIC16F87XA
2.2.2.6
PIE2 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt, and the
comparator interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0
R/W-0
CMIE
U-0
R/W-0
EEIE
R/W-0
BCLIE
U-0
U-0
R/W-0
CCP2IE
bit 0
—
—
—
—
bit 7
bit 7
bit 6
Unimplemented: Read as '0'
CMIE: Comparator Interrupt Enable bit
1= Enables the Comparator interrupt
0= Disable the Comparator interrupt
bit 5
bit 4
Unimplemented: Read as '0'
EEIE: EEPROM Write Operation Interrupt Enable bit
1= Enable EEPROM write interrupt
0= Disable EEPROM write interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1= Enable bus collision interrupt
0= Disable bus collision interrupt
bit 2-1
bit 0
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 25
MICROCHIP [ MICROCHIP ]
