PIC16F87XA
2.2.2.5
PIR1 Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
TXIF
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1= The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place.
•
I2C Slave
- A transmission/reception has taken place.
• I2C Master
- A transmission/reception has taken place.
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START condition occurred while the SSP module was idle (Multi-Master system).
- A STOP condition occurred while the SSP module was idle (Multi-Master system).
0= No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39582A-page 24
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
