PIC16F87XA
2.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 23
MICROCHIP [ MICROCHIP ]
