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PIC16F873A-I/SP 参数 Datasheet PDF下载

PIC16F873A-I/SP图片预览
型号: PIC16F873A-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
General Call Address Support ................................... 92  
Master Mode .............................................................. 93  
Operation ........................................................... 94  
INT Interrupt (RB0/INT). See Interrupt Sources.  
INTCON ............................................................................. 19  
INTCON Register ............................................................... 22  
GIE Bit ....................................................................... 22  
INTE Bit ..................................................................... 22  
INTF Bit ..................................................................... 22  
PEIE Bit ..................................................................... 22  
RBIE Bit ..................................................................... 22  
RBIF Bit ................................................................22, 42  
TMR0IE Bit ................................................................ 22  
TMR0IF Bit ................................................................. 22  
Repeated START Timing ................................... 98  
Master Mode Reception ............................................. 99  
Master Mode START Condition ................................. 97  
Master Mode Transmission ........................................ 99  
Multi-Master Communication, Bus Collision  
and Arbitration ......................................... 103  
Multi-Master Mode ................................................... 103  
Read/Write Bit Information (R/W Bit) ................... 82, 83  
Serial Clock (RC3/SCK/SCL) ..................................... 83  
Slave Mode ................................................................ 82  
Addressing ......................................................... 82  
2
Inter-Integrated Circuit. See I C.  
Internal Reference Signal ................................................ 135  
Internal Sampling Switch (Rss) Impedance ..................... 128  
Interrupt Sources ......................................................141, 151  
Interrupt-on-Change (RB7:RB4 ) ............................... 42  
RB0/INT Pin, External .....................................9, 11, 152  
TMR0 Overflow ........................................................ 152  
USART Receive/Transmit Complete ....................... 109  
Interrupts  
Bus Collision Interrupt ................................................ 26  
Synchronous Serial Port Interrupt .............................. 24  
Interrupts, Context Saving During .................................... 152  
Interrupts, Enable Bits  
Reception ........................................................... 83  
Transmission ...................................................... 83  
SLEEP Operation ..................................................... 103  
STOP Condition Timing ........................................... 102  
ICEPIC In-Circuit Emulator .............................................. 166  
ID Locations ............................................................. 141, 155  
In-Circuit Debugger .................................................. 141, 155  
Resources ................................................................ 155  
In-Circuit Serial Programming (ICSP) ...................... 141, 156  
INDF ................................................................................... 19  
INDF Register .........................................................17, 18, 29  
Indirect Addressing ............................................................ 29  
FSR Register ............................................................. 14  
Instruction Format ............................................................ 157  
Instruction Set .................................................................. 157  
ADDLW .................................................................... 159  
ADDWF .................................................................... 159  
ANDLW .................................................................... 159  
ANDWF .................................................................... 159  
BCF .......................................................................... 159  
BSF .......................................................................... 159  
BTFSC ..................................................................... 159  
BTFSS ..................................................................... 159  
CALL ........................................................................ 160  
CLRF ........................................................................ 160  
CLRW ...................................................................... 160  
CLRWDT .................................................................. 160  
COMF ...................................................................... 160  
DECF ....................................................................... 160  
DECFSZ ................................................................... 161  
GOTO ...................................................................... 161  
INCF ......................................................................... 161  
INCFSZ .................................................................... 161  
IORLW ..................................................................... 161  
IORWF ..................................................................... 161  
MOVF ....................................................................... 162  
MOVLW ................................................................... 162  
MOVWF ................................................................... 162  
NOP ......................................................................... 162  
RETFIE .................................................................... 162  
RETLW .................................................................... 162  
RETURN .................................................................. 163  
RLF .......................................................................... 163  
RRF .......................................................................... 163  
SLEEP ..................................................................... 163  
SUBLW .................................................................... 163  
SUBWF .................................................................... 163  
SWAPF .................................................................... 164  
XORLW .................................................................... 164  
XORWF .................................................................... 164  
Summary Table ........................................................ 158  
Global Interrupt Enable (GIE Bit) ........................22, 151  
Interrupt-on-Change (RB7:RB4) Enable  
(RBIE Bit) ............................................22, 152  
Peripheral Interrupt Enable (PEIE Bit) ....................... 22  
RB0/INT Enable (INTE Bit) ........................................ 22  
TMR0 Overflow Enable (TMR0IE Bit) ........................ 22  
Interrupts, Flag Bits  
Interrupt-on-Change (RB7:RB4) Flag  
(RBIF Bit) ......................................22, 42, 152  
RB0/INT Flag (INTF Bit) ............................................ 22  
TMR0 Overflow Flag (TMR0IF Bit) .....................22, 152  
K
KEELOQ Evaluation and Programming Tools ................... 168  
L
Loading of PC .................................................................... 28  
Low Voltage ICSP Programming ..................................... 156  
Low Voltage In-Circuit Serial Programming ..................... 141  
M
Master Clear (MCLR) ........................................................... 8  
MCLR Reset, Normal Operation ...............145, 147, 148  
MCLR Reset, SLEEP ................................145, 147, 148  
Master Synchronous Serial Port (MSSP).  
See MSSP.  
Master Synchronous Serial Port. See MSSP  
MCLR ............................................................................... 146  
MCLR/VPP ......................................................................... 10  
Memory Organization ........................................................ 13  
Data EEPROM Memory ............................................. 31  
Data Memory ............................................................. 14  
FLASH Program Memory .......................................... 31  
Program Memory ....................................................... 13  
MPLAB C17 and MPLAB C18 C Compilers .................... 165  
MPLAB ICD In-Circuit Debugger ..................................... 167  
MPLAB ICE High Performance Universal In-Circuit  
Emulator with MPLAB IDE ....................................... 166  
MPLAB Integrated Development Environment  
Software .................................................................. 165  
MPLINK Object Linker/MPLIB Object Librarian ............... 166  
2001 Microchip Technology Inc.  
Advance Information  
DS39582A-page 211  
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