PIC16F87XA
Timing Diagrams .............................................................. 103
A/D Conversion ........................................................ 193
Acknowledge Sequence .......................................... 102
Asynchronous Master Transmission ........................ 114
Asynchronous Master Transmission
SPI Mode Timing (Slave Mode with CKE = 1) ........... 76
SPI Slave Mode (CKE = 0) ...................................... 187
SPI Slave Mode (CKE = 1) ...................................... 187
Start-up Timer .......................................................... 182
STOP Condition Receive or Transmit Mode ............ 102
Synchronous Reception (Master Mode, SREN) ...... 122
Synchronous Transmission ..................................... 120
Synchronous Transmission (Through TXEN) .......... 120
Time-out Sequence on Power-up
(Back to Back) ......................................... 114
Asynchronous Reception ......................................... 116
Asynchronous Reception with
Address Byte Frist ................................... 118
Asynchronous Reception with
(MCLR Not Tied to VDD)
Address Detect ........................................ 118
Baud Rate Generator with Clock Arbitration .............. 96
BRG Reset Due to SDA Arbitration During
Case 1 ............................................................. 150
Case 2 ............................................................. 150
Time-out Sequence on Power-up (MCLR Tied to
START Condition ..................................... 105
Brown-out Reset ...................................................... 182
Bus Collision During a Repeated START
Condition (Case 1) ................................... 106
Bus Collision During Repeated START
VDD via RC Network) ............................... 149
Timer0 ..................................................................... 183
Timer1 ..................................................................... 183
USART Synchronous Receive (Master/Slave) ........ 191
USART Synchronous Transmission
Condition (Case 2) ................................... 106
Bus Collision During START Condition
(SCL = 0) ................................................. 105
Bus Collision During START Condition
(SDA Only) ............................................... 104
Bus Collision During STOP Condition
(Case 1) ................................................... 107
Bus Collision During STOP Condition
(Master/Slave) ......................................... 191
Wake-up from SLEEP via Interrupt .......................... 155
Watchdog Timer ...................................................... 182
TMR0 ................................................................................. 19
TMR0 Register ................................................................... 17
TMR1CS bit ....................................................................... 55
TMR1H .............................................................................. 19
TMR1H Register ................................................................ 17
TMR1L ............................................................................... 19
TMR1L Register ................................................................. 17
TMR1ON bit ....................................................................... 55
TMR2 ................................................................................. 19
TMR2 Register ................................................................... 17
TMR2ON bit ....................................................................... 59
TMRO Register .................................................................. 19
TOUTPS0 bit ..................................................................... 59
TOUTPS1 bit ..................................................................... 59
TOUTPS2 bit ..................................................................... 59
TOUTPS3 bit ..................................................................... 59
TRISA Register .................................................................. 18
TRISB Register .................................................................. 18
TRISC Register .................................................................. 18
TRISD Register .................................................................. 18
TRISE Register .............................................................18, 47
IBF Bit ........................................................................ 48
IBOV Bit ..................................................................... 48
OBF Bit ...................................................................... 48
PSPMODE Bit ........................................... 46, 47, 48, 49
TXREG .............................................................................. 19
TXREG Register ................................................................ 17
TXSTA Register ................................................................. 18
BRGH Bit ................................................................. 109
CSRC Bit ................................................................. 109
SYNC Bit ................................................................. 109
TRMT Bit .................................................................. 109
TX9 Bit ..................................................................... 109
TX9D Bit .................................................................. 109
TXEN Bit .................................................................. 109
(Case 2) ................................................... 107
Capture/Compare/PWM (CCP1 and CCP2) ............ 184
CLKOUT and I/O ...................................................... 181
Clock Synchronization ............................................... 89
First START Bit Timing .............................................. 97
2
I C Bus Data ............................................................ 189
2
I C Bus START/STOP Bits ...................................... 188
2
I C Master Mode (Reception,
7-bit Address) .......................................... 101
I C Master Mode (Transmission, 7 or
2
10-bit Address) ........................................ 100
I C Slave Mode Timing (Transmission,
2
10-bit Address) .......................................... 87
I C Slave Mode Timing (Transmission,
2
7-bit Address) ............................................ 85
I C Slave Mode Timing SEN = 1 (Reception,
2
10-bit Address) .......................................... 91
I C Slave Mode Timing with SEN = 0
2
(Reception, 10-bit Address) ....................... 86
I C Slave Mode Timing with SEN = 0
2
(Reception, 7-bit Address) ......................... 84
I C Slave Mode Timing with SEN = 1
2
(Reception, 7-bit Address) ......................... 90
Parallel Slave Port (PSP)
Read Waveforms ............................................... 50
Write Waveforms ............................................... 50
Parallel Slave Port Timing
(PIC16F874A/877A Only) ........................ 185
Power-up Timer ....................................................... 182
Repeat START Condition .......................................... 98
RESET ..................................................................... 182
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ........................ 92
Slave Synchronization ............................................... 75
Slow Rise Time (MCLR Tied to VDD via
RC Network) ............................................ 150
SPI Master Mode (CKE = 0, SMP = 0) .................... 186
SPI Mode Timing (Master Mode) ............................... 74
SPI Mode Timing (Slave Mode with CKE = 0) ........... 76
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 215
MICROCHIP [ MICROCHIP ]
