PIC16F87XA
INDEX
Crystal/Ceramic Resonator Operation (HS, XT
or LP Osc Configuration) ......................... 143
External Clock Input Operation (HS, XT
A
A/D ................................................................................... 125
Acquisition Requirements ........................................ 128
ADCON0 Register .................................................... 125
ADCON1 Register .................................................... 125
ADIF bit .................................................................... 127
ADRESH Register .................................................... 125
ADRESL Register .................................................... 125
Analog Port Pins .................................................. 47, 49
Associated Registers and Bits ................................. 131
Calculating Acquisition Time .................................... 128
Configuring Analog Port Pins ................................... 129
Configuring the Interrupt .......................................... 127
Configuring the Module ............................................ 127
Conversion Clock ..................................................... 129
Conversions ............................................................. 130
Converter Characteristics ........................................ 192
Delays ...................................................................... 128
Effects of a RESET .................................................. 131
GO/DONE bit ........................................................... 127
Internal Sampling Switch (Rss) Impedance ............. 128
Operation During SLEEP ......................................... 131
Result Registers ....................................................... 130
Source Impedance ................................................... 128
Time Delays ............................................................. 128
A/D Conversion Requirements ......................................... 193
Absolute Maximum Ratings ............................................. 171
ACKSTAT ........................................................................... 99
ADCON0 Register .............................................................. 17
ADCON1 Register .............................................................. 18
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART.
or LP Osc Configuration) ......................... 143
Interrupt Logic .......................................................... 151
MSSP
2
I C Mode ........................................................... 78
MSSP (SPI Mode) ..................................................... 69
On-Chip RESET Circuit ........................................... 145
PIC16F873A/PIC16F876A Architecture ...................... 6
PIC16F874A/PIC16F877A Architecture ...................... 7
PORTC
Peripheral Output Override
(RC 0:2, 5:7) Pins .............................. 44
Peripheral Output Override
(RC 3:4) Pins ..................................... 44
PORTD (in I/O Port Mode) ......................................... 46
PORTD and PORTE (Parallel Slave Port) ................. 49
PORTE (In I/O Port Mode) ......................................... 47
RA4/T0CKI Pin .......................................................... 40
RA5 Pin ..................................................................... 40
RB3:RB0 Port Pins .................................................... 42
RC Oscillator Mode .................................................. 144
Recommended MCLR Circuit .................................. 146
Simplified PWM Mode ............................................... 65
Timer0/WDT Prescaler .............................................. 51
Timer2 ....................................................................... 59
USART Receive ................................................115, 117
USART Transmit ...................................................... 113
Watchdog Timer ...................................................... 153
BOR. See Brown-out Reset.
BRG. See Baud Rate Generator.
BRGH Bit ......................................................................... 111
Brown-out Reset (BOR) .................... 141, 145, 146, 147, 148
BOR Status (BOR Bit) ............................................... 27
Bus Collision During a Repeated START
Condition ................................................................. 106
Bus Collision During a START Condition ........................ 104
Bus Collision During a STOP Condition .......................... 107
Bus Collision Interrupt Flag bit, BCLIF ............................... 26
Bus Collision Timing for Transmit and
ADRESH Register .............................................................. 17
ADRESL Register .............................................................. 18
Analog-to-Digital Converter. See A/D.
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) .................................... 42
AN556 (Implementing a Table Read) ........................ 28
Assembler
MPASM Assembler .................................................. 165
Asynchronous Reception
Acknowledge ........................................................... 103
Associated Registers ....................................... 116, 118
Asynchronous Transmission
C
Capture/Compare/PWM (CCP) ......................................... 61
Associated Registers
Associated Registers ............................................... 114
Capture, Compare and Timer1 .......................... 66
PWM and Timer2 ............................................... 67
Capture Mode ............................................................ 63
CCP1IF .............................................................. 63
Prescaler ........................................................... 63
CCP Timer Resources ............................................... 61
Compare
B
Banking, Data Memory ................................................. 14, 20
Baud Rate Generator ......................................................... 95
Associated Registers ............................................... 111
BCLIF ................................................................................. 26
BF ....................................................................................... 99
Block Diagram
Special Trigger Output of CCP1 ........................ 64
Special Trigger Output of CCP2 ........................ 64
Compare Mode .......................................................... 64
Software Interrupt Mode .................................... 64
Special Event Trigger ........................................ 64
Interaction of Two CCP Modules (Table) ................... 61
PWM Mode ................................................................ 65
Duty Cycle ......................................................... 65
Example Frequencies/Resolutions (Table) ........ 66
PWM Period ...................................................... 65
Special Event Trigger and A/D Conversions ............. 64
RA3:RA0 Port Pins .................................................... 39
Block Diagrams .................................................................. 56
A/D ........................................................................... 127
Analog Input Model .......................................... 128, 137
Baud Rate Generator ................................................. 95
Capture Mode Operation ........................................... 63
Comparator I/O Operating Modes ............................ 134
Comparator Output .................................................. 136
Comparator Voltage Reference ............................... 140
Compare Mode Operation ......................................... 64
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 209
MICROCHIP [ MICROCHIP ]
