PIC16F87XA
TABLE 17-9: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
SS↓ to SCK↓ or SCK↑ input
Min
Typ†
Max Units Conditions
70*
TssL2scH,
TssL2scL
Tcy
—
—
ns
71*
72*
73*
TscH
TscL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
Setup time of SDI data input to SCK edge
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
74*
75*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
TdoR
SDO data output rise time
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76*
77*
78*
TdoF
SDO data output fall time
—
10
—
25
50
ns
ns
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
10
SCK output rise time (Master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
80*
TscF
SCK output fall time (Master mode)
—
10
25
ns
ns
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
81*
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
Tcy
—
—
ns
82*
83*
TssL2doV
SDO data output valid after SS↓ edge
SS↑ after SCK edge
—
—
—
50
—
ns
ns
TscH2ssH,
TscL2ssH
1.5TCY + 40
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 17-15:
I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 17-3 for load conditions.
DS39582A-page 188
AdvanceInformation
2001 Microchip Technology Inc.