PIC16F87XA
TABLE 17-11: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
100 kHz mode
Min
4.0
0.6
Max
—
Units
µs
Conditions
100
THIGH
Clock high time
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
—
µs
Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
Tsu:sta
Thd:sta
Thd:dat
Tsu:dat
Tsu:sto
TAA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
START condition hold 100 kHz mode
time
—
After this period, the first clock
pulse is generated
400 kHz mode
—
106
107
92
Data input hold time
100 kHz mode
400 kHz mode
—
0
0.9
—
Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
STOP condition setup 100 kHz mode
time
—
400 kHz mode
—
109
110
Output valid from
clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode (400 kHz) I C bus device can be used in a standard mode (100 kHz) I C bus system, but the requirement that
Tsu:dat ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification) before the SCL line is
released.
DS39582A-page 190
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
