PIC16F/LF1946/47
5.6
Oscillator Control Registers
REGISTER 5-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1
IRCF<3:0>
R/W-0/0
SPLLEN
bit 7
U-0
—
R/W-0/0
R/W-0/0
SCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Word 1 = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Word 1 = 0:
1= 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x= 31 kHz LF
0010= 31.25 kHz MF
0011= 31.25 kHz HF(1)
0100= 62.5 kHz MF
0101= 125 kHz MF
0110= 250 kHz MF
0111= 500 kHz MF (default upon Reset)
1000= 125 kHz HF(1)
1001= 250 kHz HF(1)
1010= 500 kHz HF(1)
1011= 1 MHz HF
1100= 2 MHz HF
1101= 4 MHz HF
1110= 8 MHz or 32 MHz HF(see Section 5.2.1.4 “4X PLL”)
1111= 16 MHz HF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Timer1 oscillator
00= Clock determined by FOSC<2:0> in Configuration Word 1.
Note 1: Duplicate frequency derived from HFINTOSC.
DS41414A-page 72
Preliminary
2010 Microchip Technology Inc.
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