PIC16C63A/65B/73B/74B
FIGURE 10-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
8Ch
87h
INTCON
PIR1
GIE
PEIE
T0IE
INTE RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
PSPIF
PSPIE
ADIF
ADIE
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
(2)
PIE1
TRISC
PORTC Data Direction register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit register
SSPCON WCOL
14h
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h
TRISA
—
—
PORTA Data Direction register
D/A R/W
--11 1111 --11 1111
0000 0000 0000 0000
94h
SSPSTAT
SMP
CKE
P
S
UA
BF
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
2000 Microchip Technology Inc.
DS30605C-page 59
MICROCHIP [ MICROCHIP ]
