PIC16C63A/65B/73B/74B
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
10.0 SYNCHRONOUS SERIAL PORT
(SSP) MODULE
Internal
Data Bus
10.1 SSP Module Overview
Read
Write
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
SSPBUF reg
SSPSR reg
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
RC4/SDI/SDA
RC5/SDO
Shift
Clock
bit0
tion on the SSP module can be found in the PICmicro™
Mid-Range
(DS33023).
MCU
Family
Reference Manual
Control
Enable
SS
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment.”
RA5/SS/AN4
Edge
Select
10.2 SPI Mode
2
This section contains register definitions and opera-
tional characteristics of the SPI module.
Clock Select
SSPM3:SSPM0
4
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
TMR2 Output
2
Edge
Select
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
Additionally, a fourth pin may be used when in a Slave
mode of operation:
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• SDI must have TRISC<4> set
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3> cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
• Clock edge (output data on rising/falling edge of
SCK)
• ADCON1 must configure RA5 as a digital I/O pin.
.
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
2000 Microchip Technology Inc.
DS30605C-page 55
MICROCHIP [ MICROCHIP ]
