欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16C74B-04/P 参数 Datasheet PDF下载

PIC16C74B-04/P图片预览
型号: PIC16C74B-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS微控制器 [28/40-Pin 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管可编程只读存储器时钟
文件页数/大小: 184 页 / 2122 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16C74B-04/P的Datasheet PDF文件第56页浏览型号PIC16C74B-04/P的Datasheet PDF文件第57页浏览型号PIC16C74B-04/P的Datasheet PDF文件第58页浏览型号PIC16C74B-04/P的Datasheet PDF文件第59页浏览型号PIC16C74B-04/P的Datasheet PDF文件第61页浏览型号PIC16C74B-04/P的Datasheet PDF文件第62页浏览型号PIC16C74B-04/P的Datasheet PDF文件第63页浏览型号PIC16C74B-04/P的Datasheet PDF文件第64页  
PIC16C63A/65B/73B/74B  
The SSPCON register allows control of the I2C opera-  
tion. Four mode selection bits (SSPCON<3:0>) allow  
one of the following I2C modes to be selected:  
I2C Slave mode (7-bit address)  
I2C Slave mode (10-bit address)  
I2C Slave mode (7-bit address), with START and  
STOP bit interrupts enabled to support firmware  
Master mode  
I2C Slave mode (10-bit address), with START and  
STOP bit interrupts enabled to support firmware  
Master mode  
I2C START and STOP bit interrupts enabled to  
support firmware Master mode, Slave is idle  
2
10.3 SSP I C Operation  
The SSP module in I2C mode fully implements all slave  
functions, except general call support, and provides  
interrupts on START and STOP bits in hardware to  
facilitate firmware implementation of the master func-  
tions. The SSP module implements the standard mode  
specifications as well as 7-bit and 10-bit addressing.  
Two pins are used for data transfer, the RC3/SCK/SCL  
pin, which is the clock (SCL), and the RC4/SDI/SDA  
pin, which is the data (SDA). The user must configure  
these pins as inputs or outputs through the  
TRISC<4:3> bits. External pull-up resistors for the SCL  
and SDA pins must be provided in the application cir-  
cuit for proper operation of the I2C module.  
Selection of any I2C mode with the SSPEN bit set,  
forces the SCL and SDA pins to be open drain, pro-  
vided these pins are programmed to inputs by setting  
the appropriate TRISC bits.  
The SSP module functions are enabled by setting SSP  
enable bit SSPEN (SSPCON<5>).  
Additional information on SSP I2C operation can be  
found in the PICmicroMid-Range MCU Family Ref-  
erence Manual (DS33023).  
FIGURE 10-5:  
SSP BLOCK DIAGRAM  
(I2C MODE)  
Internal  
Data Bus  
10.3.1  
SLAVE MODE  
Read  
Write  
In Slave mode, the SCL and SDA pins must be config-  
ured as inputs (TRISC<4:3> set). The SSP module will  
override the input state with the output data when  
required (slave-transmitter).  
SSPBUF reg  
RC3/SCK/SCL  
Shift  
Clock  
When an address is matched or the data transfer after  
an address match is received, the hardware automati-  
cally generates the acknowledge (ACK) pulse, and  
then loads the SSPBUF register with the received  
value currently in the SSPSR register.  
SSPSR reg  
RC4/SDI/  
SDA  
MSb  
LSb  
Match Detect  
Addr Match  
There are certain conditions that will cause the SSP  
module not to give this ACK pulse. They include (either  
or both):  
SSPADD reg  
START and  
a) The buffer full bit BF (SSPSTAT<0>) was set  
before the transfer was received.  
Set, Reset  
S, P bits  
(SSPSTAT reg)  
STOP bit Detect  
b) The overflow bit SSPOV (SSPCON<6>) was set  
before the transfer was received.  
In this case, the SSPSR register value is not loaded  
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.  
Table 10-2 shows what happens when a data transfer  
byte is received, given the status of bits BF and  
SSPOV. The shaded cells show the condition where  
user software did not properly clear the overflow condi-  
tion. Flag bit BF is cleared by reading the SSPBUF  
register while bit SSPOV is cleared through software.  
The SSP module has five registers for I2C operation.  
These are the:  
SSP Control Register (SSPCON)  
SSP Status Register (SSPSTAT)  
Serial Receive/Transmit Buffer (SSPBUF)  
SSP Shift Register (SSPSR) - not directly accessible  
SSP Address Register (SSPADD)  
The SCL clock input must have minimum high and low  
times for proper operation. The high and low times of  
the I2C specification, as well as the requirement of the  
SSP module, is shown in timing parameter #100 and  
parameter #101.  
DS30605C-page 60  
2000 Microchip Technology Inc.