PIC16C63A/65B/73B/74B
FIGURE 13-5:
INTERRUPT LOGIC
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Yes
Yes
13.5.1
INT INTERRUPT
13.5.3
PORTB INTERRUPT-ON-CHANGE
The external interrupt on RB0/INT pin is edge trig-
gered: either rising if bit INTEDG (OPTION_REG<6>)
is set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 13.8 for details on SLEEP mode.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
13.5.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (see Section 6.0).
DS30605C-page 94
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
