PIC16C63A/65B/73B/74B
TABLE 9-4:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
0Dh
8Ch
8Dh
87h
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0000 000x 0000 000u
PSPIF(1) ADIF(2)
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
PIR2
—
—
PIE1
PSPIE(1) ADIE(2)
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
—
TMR2IE
—
PIE2
—
—
TRISC
PORTC Data Direction register
0Eh
0Fh
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
CCP1X
CCP1Y
CCP1M3
CCP2M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
1Bh
1Ch
1Dh
Capture/Compare/PWM register2 (LSB)
Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
—
—
CCP2X
CCP2Y
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear.
2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear.
TABLE 9-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
0Dh
8Ch
8Dh
87h
INTCON
PIR1
GIE
PEIE
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
0000 0000 0000 0000
---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
PSPIF(1) ADIF(2)
TMR1IF
CCP2IF
TMR1IE
CCP2IE
PIR2
—
—
PIE1
PSPIE(1) ADIE(2)
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
—
TMR2IE
—
PIE2
—
—
TRISC
TMR2
PR2
PORTC Data Direction register
Timer2 Module’s register
11h
92h
Timer2 Module’s Period register
12h
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1
CCP2M3 CCP2M2 CCP2M1
CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
1Bh
Capture/Compare/PWM register2 (LSB)
1Ch
1Dh
Legend:
CCPR2H Capture/Compare/PWM register2 (MSB)
CCP2CON CCP2X CCP2Y
xxxx xxxx uuuu uuuu
—
—
CCP2M0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605C-page 54
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
